Dustin C. Hatch
31d8a98f64
In effort to support different builds of Aimee OS using the same scripts, without necessarily having to fork this repository, the build system now supports a `CONFIGDIR` setting. When this variable is set, files defining the target environment, such as the lists of packages to install, the kernel configuration, the Portage configuration, etc. are found in the path it specifes. The reference build, for the Home Assistant Yellow board, is configured in the `yellow` directory. To build it, run: ```sh CONFIGDIR=yellow ./vm-build.sh ```
177 lines
6.3 KiB
Diff
177 lines
6.3 KiB
Diff
From c70926d8b8ad11b8e489e92a8ca9ca93fb201595 Mon Sep 17 00:00:00 2001
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Message-Id: <c70926d8b8ad11b8e489e92a8ca9ca93fb201595.1668448794.git.stefan@agner.ch>
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In-Reply-To: <135d886b4e5077c8fa96a5449a70d81ae9c1c3d0.1668448794.git.stefan@agner.ch>
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References: <135d886b4e5077c8fa96a5449a70d81ae9c1c3d0.1668448794.git.stefan@agner.ch>
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From: Stefan Agner <stefan@agner.ch>
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Date: Fri, 24 Sep 2021 00:27:39 +0200
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Subject: [PATCH] nvme: translate virtual addresses into the bus's address
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space
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So far we've been content with passing physical/CPU addresses when
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configuring memory addresses into NVMe controllers, but not all
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platforms have buses with transparent mappings. Specifically the
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Raspberry Pi 4 might introduce an offset to memory accesses incoming
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from its PCIe port.
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Introduce nvme_virt_to_bus() and nvme_bus_to_virt() to cater with these
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limitations, and make sure we don't break non DM users.
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For devices where PCIe's view of host memory doesn't match the memory
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as seen by the CPU.
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A similar change has been introduced for XHCI controller with
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commit 1a474559d90a ("xhci: translate virtual addresses into the bus's
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address space").
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Signed-off-by: Stefan Agner <stefan@agner.ch>
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---
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drivers/nvme/nvme.c | 31 +++++++++++++++++--------------
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drivers/nvme/nvme.h | 8 ++++++++
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2 files changed, 25 insertions(+), 14 deletions(-)
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diff --git a/drivers/nvme/nvme.c b/drivers/nvme/nvme.c
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index 352c94ea91..fdfc49677b 100644
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--- a/drivers/nvme/nvme.c
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+++ b/drivers/nvme/nvme.c
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@@ -66,7 +66,7 @@ static int nvme_setup_prps(struct nvme_dev *dev, u64 *prp2,
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buffer += (page_size - offset);
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if (length <= page_size) {
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- *prp2 = (u64)buffer;
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+ *prp2 = nvme_virt_to_bus(dev, buffer);
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return 0;
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}
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@@ -91,16 +91,16 @@ static int nvme_setup_prps(struct nvme_dev *dev, u64 *prp2,
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i = 0;
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while (nprps) {
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if ((i == (prps_per_page - 1)) && nprps > 1) {
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- u64 next_prp_list = (u64)prp_pool + page_size;
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- *(prp_pool + i) = cpu_to_le64(next_prp_list);
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+ u64 next = nvme_virt_to_bus(dev, prp_pool + page_size);
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+ *(prp_pool + i) = cpu_to_le64(next);
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i = 0;
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prp_pool += page_size;
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}
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- *(prp_pool + i++) = cpu_to_le64((u64)buffer);
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+ *(prp_pool + i++) = cpu_to_le64(nvme_virt_to_bus(dev, buffer));
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buffer += page_size;
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nprps--;
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}
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- *prp2 = (u64)dev->prp_pool;
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+ *prp2 = nvme_virt_to_bus(dev, dev->prp_pool);
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flush_dcache_range((ulong)dev->prp_pool, (ulong)dev->prp_pool +
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num_pages * page_size);
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@@ -353,6 +353,7 @@ static int nvme_configure_admin_queue(struct nvme_dev *dev)
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int result;
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u32 aqa;
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u64 cap = dev->cap;
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+ u64 dma_addr;
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struct nvme_queue *nvmeq;
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/* most architectures use 4KB as the page size */
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unsigned page_shift = 12;
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@@ -393,8 +394,10 @@ static int nvme_configure_admin_queue(struct nvme_dev *dev)
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dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
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writel(aqa, &dev->bar->aqa);
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- nvme_writeq((ulong)nvmeq->sq_cmds, &dev->bar->asq);
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- nvme_writeq((ulong)nvmeq->cqes, &dev->bar->acq);
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+ dma_addr = nvme_virt_to_bus(dev, nvmeq->sq_cmds);
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+ nvme_writeq(dma_addr, &dev->bar->asq);
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+ dma_addr = nvme_virt_to_bus(dev, nvmeq->cqes);
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+ nvme_writeq(dma_addr, &dev->bar->acq);
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result = nvme_enable_ctrl(dev);
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if (result)
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@@ -420,7 +423,7 @@ static int nvme_alloc_cq(struct nvme_dev *dev, u16 qid,
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memset(&c, 0, sizeof(c));
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c.create_cq.opcode = nvme_admin_create_cq;
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- c.create_cq.prp1 = cpu_to_le64((ulong)nvmeq->cqes);
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+ c.create_cq.prp1 = cpu_to_le64(nvme_virt_to_bus(dev, nvmeq->cqes));
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c.create_cq.cqid = cpu_to_le16(qid);
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c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
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c.create_cq.cq_flags = cpu_to_le16(flags);
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@@ -437,7 +440,7 @@ static int nvme_alloc_sq(struct nvme_dev *dev, u16 qid,
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memset(&c, 0, sizeof(c));
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c.create_sq.opcode = nvme_admin_create_sq;
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- c.create_sq.prp1 = cpu_to_le64((ulong)nvmeq->sq_cmds);
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+ c.create_sq.prp1 = cpu_to_le64(nvme_virt_to_bus(dev, nvmeq->sq_cmds));
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c.create_sq.sqid = cpu_to_le16(qid);
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c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
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c.create_sq.sq_flags = cpu_to_le16(flags);
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@@ -458,14 +461,14 @@ int nvme_identify(struct nvme_dev *dev, unsigned nsid,
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memset(&c, 0, sizeof(c));
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c.identify.opcode = nvme_admin_identify;
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c.identify.nsid = cpu_to_le32(nsid);
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- c.identify.prp1 = cpu_to_le64((u64)buffer);
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+ c.identify.prp1 = cpu_to_le64(nvme_virt_to_bus(dev, buffer));
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length -= (page_size - offset);
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if (length <= 0) {
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c.identify.prp2 = 0;
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} else {
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buffer += (page_size - offset);
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- c.identify.prp2 = cpu_to_le64((u64)buffer);
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+ c.identify.prp2 = cpu_to_le64(nvme_virt_to_bus(dev, buffer));
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}
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c.identify.cns = cpu_to_le32(cns);
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@@ -490,7 +493,7 @@ int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid,
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memset(&c, 0, sizeof(c));
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c.features.opcode = nvme_admin_get_features;
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c.features.nsid = cpu_to_le32(nsid);
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- c.features.prp1 = cpu_to_le64((u64)buffer);
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+ c.features.prp1 = cpu_to_le64(nvme_virt_to_bus(dev, buffer));
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c.features.fid = cpu_to_le32(fid);
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ret = nvme_submit_admin_cmd(dev, &c, result);
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@@ -516,7 +519,7 @@ int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11,
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memset(&c, 0, sizeof(c));
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c.features.opcode = nvme_admin_set_features;
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- c.features.prp1 = cpu_to_le64((u64)buffer);
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+ c.features.prp1 = cpu_to_le64(nvme_virt_to_bus(dev, buffer));
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c.features.fid = cpu_to_le32(fid);
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c.features.dword11 = cpu_to_le32(dword11);
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@@ -771,7 +774,7 @@ static ulong nvme_blk_rw(struct udevice *udev, lbaint_t blknr,
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c.rw.slba = cpu_to_le64(slba);
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slba += lbas;
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c.rw.length = cpu_to_le16(lbas - 1);
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- c.rw.prp1 = cpu_to_le64(temp_buffer);
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+ c.rw.prp1 = cpu_to_le64(nvme_virt_to_bus(dev, temp_buffer));
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c.rw.prp2 = cpu_to_le64(prp2);
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status = nvme_submit_sync_cmd(dev->queues[NVME_IO_Q],
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&c, NULL, IO_TIMEOUT);
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diff --git a/drivers/nvme/nvme.h b/drivers/nvme/nvme.h
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index bc1d612dde..f52103c009 100644
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--- a/drivers/nvme/nvme.h
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+++ b/drivers/nvme/nvme.h
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@@ -7,8 +7,11 @@
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#ifndef __DRIVER_NVME_H__
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#define __DRIVER_NVME_H__
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+#include <phys2bus.h>
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#include <asm/io.h>
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+#define nvme_to_dev(_dev) _dev->udev
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+
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struct nvme_id_power_state {
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__le16 max_power; /* centiwatts */
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__u8 rsvd2;
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@@ -705,4 +708,9 @@ int nvme_init(struct udevice *udev);
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*/
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int nvme_shutdown(struct udevice *udev);
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+static inline dma_addr_t nvme_virt_to_bus(struct nvme_dev *dev, void *addr)
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+{
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+ return dev_phys_to_bus(nvme_to_dev(dev)->parent, virt_to_phys(addr));
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+}
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+
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#endif /* __DRIVER_NVME_H__ */
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--
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2.38.1
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